8-Bit Multipler Using Recoded Redix-8 Booth’s Algorithm Using Verilog Hdl

Abstract

The instruction sets of the DSP digital signal processing typically includes two fundamental operations – multiplication and addition, commonly referred to as multiply and accumulate (MCA). MCA functional unit must be implemented efficiently and must give high performance. For MCA unit to give high performance multiplication should be done efficiently and in faster. For sequential multiplication booth’s recoding of bits are performed so that multiple operations can be performed in single clock cycle. Radix-8 multiplication set in which 4 bits are encoded simultaneously reduce cycle needed to perform multiplication by half eventually increase the speed of multiplication by double.