Improving Very Large Scale Integration Physical Domain Design

Abstract

Subdividing a large electronic system into more manageable pieces is an essential first step in the planning process. Each subsystem is created independently and concurrently to shorten the design cycle. To simplify a complex system, its components are divided up via a partitioning technique. A crucial step in the physical construction of the circuit is partitioning. To build complex digital logic circuits, it is sometimes necessary to partition multi-million transistor circuits into manageable pieces. Thus, partitioning is both an algorithmic strategy for addressing difficult and complex combinatorial optimization problems (e.g., in logic or layout synthesis) and a design challenge for breaking down bigger systems into smaller sub-systems that include interconnected components. Specific goals, either to be achieved independently or cumulatively, inform the creation of partitioning. In this dissertation, we want to decrease the Mincut between the partitions, decrease the inter-partition latency, optimize the sleep duration of the partitions to minimize power consumption, and determine the various temporal complexity of the suggested methods. We also pursue these four aims.