1 GHz High Sensitivity Differential Current Comparator for High Speed ADC

Authors

  • B S Patro
  • Suman Biswas
  • Indrani Roy
  • B. Vandana

Keywords:

current comparator; Wilson's current mirror comparator; dynamic latch; kickback noise; ADC.

Abstract

A fast responding low power differential current comparator operating at 1 GHz clock speed
is presented in this paper. The comparator proposed in this paper is composed of three
stages. The paper presents a modified version of Wilson's current mirror comparator for the
detection of very low current. This serves as the first stage which is current to voltage
conversion followed by comparison stage and buffer stage. Working at a supply of 1.8 V, the
comparator is capable of sensing a minimum difference of 4 nA for 6 µA reference current. In
addition to low power dissipation this circuit shows a swift response resulting in a
propagation delay which is less than 0.9 ns for an input difference of 0.1 µA. The current
comparator is simulated using Cadence Virtuoso Analog Design Environment 0.18 µm
CMOS technology.

Published

2017-02-12

Issue

Section

Articles