Design of EDDR Architecture Based on Approximate Arithmetic Adders

Abstract

This paper presents the design and simulation of design of EDDR architecture based on
approximate arithmetic adders. Dynamic reconfigurable approximate arithmetic units are
used to generate and get the original data. The motion estimation (ME) plays a significant
role in a video coder, testing such a module is of main concern. Whereas focusing on the
testing of ME in a video coding system this work presents an EDDR (error detection and data
recovery) has been designed for excessive performance in software program implementation.
To stumble on errors within the processing factors (PE) based totally on residue and
quotient(RQ)code and for this reason, improves detection and facts recovery via the use of
the proposed EDDR design for video coding testing application effectively. The design of the
gadget is implemented and the language used to put in writing the code is Verilog after which
is simulated using Modelsim6.4a. The software device used is Xilinx ISE design match 14.7.