Design and Implementation of Low Power Ring and Johnson Counter using Transistor Resizing Technology by VHDL

Abstract

In SOC’s (System on Chip), numerous systems have been utilized to decrease the dynamic
power of by and the large circuit which forces physical limitations or depends intensely on
rationale capacity of the circuit. Dynamic power is primarily devoured by clock organize. So
methods to lessen the power in clock arrange really limit the dynamic power altogether.There
is a prerequisite of supplanting the flip-flop with a more proficient circuit which has same
usefulness while accomplishing low power, zone, and vigor to PVT varieties. The pulsed latch
system is a standout amongst the most doable answers for this issue. In this work, the
execution of the ring counter is enhanced utilizing a pulsed latch method. In rapid and low
power VLSI applications where overwhelming pipelining is utilized, there is a necessity of
low power edge activated flip-flops. The relocation from flip-flop to pulsed latch has turned
out to be an incredible accomplishment in low power VLSI application.The design will be
replicated and blended in Xilinx 14.1i ISE.