Design and Implementation of BCD Adder Using Parallel Prefix Technique

Abstract

In this paper, the necessities of commercial electronics circuits, as well as low power and time delay, have been considered, and for decimal operations, decimal adders and the QCA technique have been skillfully applied for future advancements. To test the performance of the adder circuit, various clocking schemes were used. The parallel prefix technique is utilized in this research to develop an efficient adder with many operations. This helps to reduce the area occupied and overall delay without sacrificing performance or power consumption. There are different types of methods for the path of carry propagation in adder in which one is parallel prefix adder. The carry propagation through the stages slows down as the number of stages grows. The main objective of this paper is to design BCD* using parallel prefix technique to increase the speed in the digital signal processor while performing addition. Various adder is analyzed and compared on the basis of areas, power, and delay.