Efficient 10T SRAM Design Enhancing Read-Write Performance with Minimizing Power Consumption

Abstract

Power consumption, area requirements, and overall performance are the three main aspects that must be considered when building a Static Random Access Memory (SRAM) circuit. This study recommends a 10T SRAM design with improved read/write performance and minimal power consumption. The suggested circuit operates in single-end mode when being written to, and differential mode when being read from. LTSpice software uses the 180nm technology to calculate the metrics of the proposed 10T cell, which are decreased by 24.66%, including read stability, static noise margin (SNM), data retention voltage (DRV), power dissipation, standby (battery) power, and read energy. Since SRAM makes up a significant portion of cache, efforts to reduce the amount of energy it uses have long been explored. The demand for low-voltage, low-power SRAM has increased as low-power digital devices have grown exponentially. SRAM circuits require a hold voltage to preserve the memory state since they lose data during the power-down state. As a result, there is high energy loss and leakage power. To address these problems, several strategies, including power gating, have been suggested. The stability of a cell is significantly influenced by its static noise margin (SNM). At various stages of the design cycle, multiple approaches have been proposed to overcome this issue.