Floating Point Multiplier using Parallel Multiplier Technique

Abstract

Floating point arithmetic has various applications in DSP, digital computers, and robots because it can represent very small numbers, enormous numbers, and signed/unsigned integers. Despite its complexity, floating point arithmetic is becoming increasingly widely implemented. The IEEE 754 standard offers two methods for expressing floating point numbers. IEEE 754 and IEEE 854 are the two ideals used to represent floating point numbers. To represent floating point integers, the IEEE 854 standard uses a variable bit length. IEEE 754 is the most widely used standard for encoding floating point values in computers, with four levels of precision. It's a fixed-point representation. Fixed point algorithms should make up the majority of FPGA algorithms. Floating point operations have many applications in various industries due to their huge dynamic series, permissive operation limitations, and high precision. Sign field, Exponent field, and Mantissa field, also known as Significant, all of which are 1 bit, 8 bit (for SPFP) or 11 bit (for DPFP) and 23 bits (for SPFP) or 52 bits (for DPFP) respectively, are used to store floating point values in memory.  For this, we used a number of adders, including the Carry select adder, which is renowned as the fastest of the classic adders. We're using a carry choice adder, which is better than ripple carry and look ahead carry parallel adders.