Comparative Analysis of Full-Adder Using Conventional XNOR and NEO-XNOR Logic

Abstract

Full-Adders are the basic blocks of on-chip integrations. Most of the parts of CPU like functions of ALU and processors include Snapdragon, Exynos, or Intel Pentium. In this paper, we proposed a novel technique of XNOR design implemented at full-adders and compared their operating behavior with the conventional XNOR Full-Adder design. We have simulated every simple logic design of XNOR/NOR in CADENCE VIRTUOSO at 180nm technology for full-adders and ripple carry adders with different input patterns, frequencies, and voltages.