2 Bit Ternary ALU Slice Design and Implementation

Abstract

The architecture, design, and implementation of a two-bit ternary ALU (T-ALU) slice are described in this study. The proposed ALU is designed for two-bit operations and can be cascaded to do n bit operations. For ternary mathematics and good judgement circuits, this ALU is developed using C-MOS ternary logic gates (T-Gates). The proposed ALU is suitable for LSI / VLSI implementation since ternary gates are constructed using enhancement/depletion MOSFET generation. In classic ternary common sense implementation, the best levels, i.e. decoder and T-gates, are required, as opposed to three ranges, i.e. decoder, binary gates, and encoder.