Area Efficient Design of Shift Register through Comparative Analysis of Latches and Flip-Flops

Abstract

This work presents a energy and area-efficient shift register using pulsed latches. Energy
consumption plays an important role in digital systems, because of the requirement to
dissipate this energy in high-density circuits and the battery life need to be extended in
portable systems such as devices with wireless communication capabilities. Flip-flops
consume more energy in digital circuits. In flip flops timing problem occurs due to the
redundancy, when the input and the output are in the same state. Several low-power
techniques are available but all of them incur transistor-count penalties, leading to an
increase in size. In this work the power and energy efficiency of several CMOS master–slave
flip-flops and latches are designed and investigated. Among the flip-flops and latches
compared, the proposed SSASPL (Static Sense Amplifier with Shared Pulse Generator)
circuit is found to be the best energy and area efficient and this circuit is used to design a
shift register. This method solves the timing problem through the use of multiple non-overlap
delayed pulsed clock signals instead of single pulsed clock signal. The shift register designed
by grouping the latches to several sub shift registers and using additional temporary storage
latches but uses a small number of the pulsed clock signals. A 16-bit shift register using
pulsed latches was fabricated using a 0.18 µm CMOS process with VDD = 1.8v. The proposed
shift register saves 52% area and 44% power compared to the conventional shift register
with flip-flops.