Design and Implementation of High Speed and Area Optimized Vedic Processor for Embedded Systems
Keywords:
Accumulator, Arithmetic Logic Unit (ALU), Central Processing Unit (CPU), Multiply, Reduced Instruction Set Computer (RISC), Vedic, Very High-Speed Integrated Circuit Hardware Description Language (VHDL)Abstract
The proposed work on the design and implementation of a High-Speed and Area-Optimized Vedic Processor for Embedded Systems appears promising. Here's an outline that we might find useful for organizing our work. Discuss briefly the growing need for high-performance embedded systems and the crucial role of processors. Summarize prior research on Vedic Processors, highlighting major features and optimizations gained by earlier researchers. The exact Vedic mathematics ideas and sutras that we propose to exploit in our processor design. Detail tactics for obtaining high-speed operations in the CPU, taking into account parallelism, pipelining, and other optimization approaches. As the computational complexity of tiny battery-powered devices develops, this study addresses the need for a fast 16-bit RISC processor. The emphasis is on boosting processor capabilities by integrating a Multiply-Accumulator (MAC) unit based on Vedic mathematics. The inclusion of a new instruction set involves VHDL-based changes to the processor's architecture, to ensure simplicity and total compatibility with the current structure. This study describes an innovative strategy for enhancing the capabilities of modest 16-bit RISC processors by including a Vedic mathematics-based Multiply-Accumulator (MAC) unit. The objective is to improve processor functionality by providing a new instruction set, which will be performed through VHDL-based changes to the CPU's design. The newly designed instruction set keeps its structure basic, ensuring complete compatibility with the previous architecture. A 16-bit pipelined system based on Harvard design has several components in its pipeline, comprising register access, arithmetic execution, front-end logic execution, instruction fetch, and decode. The simulation results demonstrate the validity of the proposed design, demonstrating effective verification and synthesis of the MAC architecture on an FPGA platform.
