A 32nm High Read Margin Single-Ended 9T SRAM Cell

Abstract

This work presents a single-ended 9T static random-access memory (SRAM) cell. One side of the latch employs Schmitt-trigger (ST) inverter for achieving high read stability. Single ended read/write feature of the cell has resulted in low switching power consumption. TSPICE simulation is carried out using 32nm predictive technology model (PTM) to extract various parameters of the proposed cell. Simulation results show that the read power consumption of the proposed cell is 2.74x lower as compared to 6T cell at 0.6V. Proposed circuit shows 2.09x improvement in read static noise margin (RSNM) as compared to conventional 6T cell. Proposed design dissipates 2.6x lesser standby power than convention 6T cell at 0.8V.