An Efficient BCD Digit Multiplier Using Different Binary-to-BCD Converters

Abstract

Numerous business applications, such as economic analysis, tax computation, money exchange, insurance, and accountancy, need use of decimal multiplication. Binary coded decimal (BCD) is a type of binary encodings where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD can encode from 0 to 9 in a decimal number. The binary coded decimal (BCD) digit multiplier consists of two main blocks, binary multiplier, and Partial Product Binary-to-BCD converter. Binary-to-BCD conversion is the fundamental block of BCD digit multiplier. In this work we describe three Binary-to-BCD conversion algorithms. They are i) Double dabble algorithm, ii) Split-based Algorithm, iii) Lookup table based algorithm. Later, these algorithms are then utilized to design an efficient binary coded decimal digit multiplier. All the designs are described using Verilog HDL and simulated in Xilinx ISE 14.5. From the results, we observe that binary coded decimal (BCD) digit multiplier with Double dabble algorithm is the most efficient with maximum operating frequency and low power dissipation when compared binary coded decimal (BCD) digit multiplier with other algorithms.