An Advanced Technique for Performance Improvement in VLSI Interconnects

Abstract

Practically interconnecting wires can no longer behave as simple resistor when it enters into deep submicron technology. These interconnects offer some parasitic effects such as capacitance and inductance, due to which signal transition delays increases. Interconnect delays plays a significant role in designing of high-performance VLSI circuit. Many researchers have proposed different types of repeater circuits to avoid the transition delays in VLSI design, but those repeater designs do not fulfill the future design requirements. Hence in this work, the Schmitt trigger is used as a repeater for the improvement of transition delay and power dissipation in on-chip interconnect wires. The more favorable advantage of the Schmitt trigger is, it is having variable threshold voltage; hence the threshold voltage can be chosen to any equal of voltage. Hence Schmitt trigger has been developed to increase the switching speed compared to the conventional buffer, hence it reduces the propagation delays. The proposed Schmitt trigger method is first designed and compared with the conventional buffer. Further, the proposed Schmitt trigger method is inserted for linear interconnects of various lengths and then inserted on buses which are groups of interconnects. Further we analyzed the proposed method by dividing interconnect into different segments. It has been observed that the proposed design is a good improvement in terms of performance parameters such as transition delays and offers less power dissipation than conventional buffers.