Low Power 4-2 Compressor Design using Complementary Metal-Oxide Semiconductor and Memristor

Abstract

This paper presents a low power 4-2 compressor circuit with the fastest operating capabilities for arithmetic operation in VLSI system. A newly designed XNOR gate is used to construct a Full Adder circuit, then the concept of the Adder circuit assisted to design the compressor circuit with a minimum number of transistors. Consequently, the overhead area shrinks about 10%. Time delay, power consumption and power-delay product (PDP) of proposed 4-2 compressor circuit have been compared with previously presented circuits and the proposed circuit is verified to have the minimum power consumption ranges from 0.050 uW to 0.055 uW and the lowest time delay ranges from 0.68ps to 0.695ps. Moreover, the PDP of the proposed cell declined to 0.0357(10-18 J), which is a very significantly decrease from its nearest equals. Widespread circuit simulations have been performed by using LTSPICE based on 7nm PTM CMOS technology and also Cadence Spectre Simulator with 45nm standard CMOS technology.