A Disturb-Free 9T SRAM Cell for Low Power Applications

Abstract

A read disturb-free 9T static random-access memory (SRAM) cell for low power applications is presented. The cell provides high read stability due to use of isolated read buffer. TSPICE simulation is done using 32nm predictive technology model (PTM) to extract various parameters. Simulation results show that proposed circuit achieves 2.95x larger read static noise margin (RSNM) as compared to conventional 6T cell at 0.8V. Read power of the proposed cell is 0.54x as that of conventional 6T cell. Leakage power of the proposed design is 0.34x of the convention 6T cell at 0.8V.