Implementation of BCD Floating Point Multiplier using Vedic Maths

Abstract

In this thesis BCD Floating Point Multiplier with Brent Kung adder with less is designed with less gate count and delay. In the xilinx ISE 14.7 design tool set, the design is modelled in Verilog HDL, simulated, and synthesised. The synthesis report provided by the Xilinx ISE 14.7 design tool package is used to do the comparisons. In terms of latency and gate count, the findings reveal that the BCD Floating Point Multiplier with Brent Kung Adder performs better.