Leakage Power Reduction of Static RAMs using Power Gating Technique

Abstract

The paper presents a 6T SRAM based on DG-MOSFET and Sleep Transistor for leakage current reduction. The basic 6-T Static RAM has been designed using the conventional transistor technology of 90nm channel width. We have used a DG-MOSFET for reducing the threshold voltage and so the power consumption. On the circuit level, the static power dissipation has been considered. Reduction of leakage current is done by using Sleep Transistor technique. A modified version of the Static RAM with the Double Gate MOSFET and the leakage reducing Sleep transistor device has been also designed and implemented. The designing and simulation tool we used is Cadence virtuoso. The transient, dc and parametric analysis provide the results. The analysis of the static RAM has been tested for proper functioning in terms of the dc and transient response. The variation of the w/l ratio has been carried out to check the leakage reduction of the circuit. It has been shown that proposed circuit performs substantially better compared to the conventional SRAM in regards of leakage reduction.