Design and Analysis of 6T SRAM in 90nm
https://doi.org/10.46610/JOVDSP.2023.v09i03.001
Keywords:
Conventional, Gated VDD, Power consumption, Processors, Speed, Stability, Static random access memory (SRAM)Abstract
This paper aims to design and analyse 6T SRAM in 90nm. All of us desire improved speed for our devices, such as laptops, mobile phones, and computers. Not only our processors but also our memory devices should be fast. In today’s world, more than 80% of chips contain memory elements. Memories are the most valuable part of convenient battery operated digital devices. So, to improve, there are various techniques to design and analyse the SRAM. In this, a conventional SRAM is designed, and the stability, speed, and power consumption are analysed and the gated VDD SRAM is also designed, and the stability, speed, and power consumption are analysed. Based on the resulting and simulated outputs, the Gated VDD SRAMS consumes 8.41% less power than Conventional SRAM and the delay of Gated VDD SRAM is also reduced by 18.052%. Simulations are implemented using the Cadence Virtuoso tool with 90nm technology.
