Analyzing Polar Decoding Approaches: A Comparative Study

Abstract

In this paper, we present three methodologies for implementing polar decoders, which are error-correcting codes widely, used in modern communication systems while polar codes show great promise, their implementation can be challenging due to their high computational complexity, which can negatively impact latency and throughput. To address this challenge, we propose three efficient implementations of polar decoders, including processing element-based design, component code-based design, and a special node-based design that identifies specific bit patterns to reduce decoding complexity. We evaluate our proposed decoders by implementing and simulating them using Verilog HDL on the Xilinx platform and compare their performance against existing research papers. Our results demonstrate significant improvements in terms of latency, area throughput, and power dissipation, making them highly suitable for modern communication systems. The special node-based decoder demonstrated the best performance, accomplishing a latency of 32.532ns and a throughput of 245.91 Mbps, using 393 LUTs and an on-chip power dissipation of 3.921 watts. The processing element-based decoder achieved a latency of 40.41 ns and a throughput of 197.79 Mbps, using 445 LUTs and an on-chip power dissipation of 4.142 watts. The component code-based decoder achieved a latency of 33.29 ns and a throughput of 240.27 Mbps, using 470 LUTs and an on-chip power dissipation of 4.933 watts.