Implementation of HD-SPWM Generation for Voltage Source Inverter Applications

DOI: https://doi.org/10.46610/JOVDSP.2022.v08i02.002

Abstract

The digital implementation of High-Definition Sinusoidal Pulse Width Modulation (HD-SPWM) achieves a higher accuracy  and simplifies hardware design. To generate the digital PWM signal a single BRAM(Block Random Access Memory) is used. The memory allocation of the targeted FPGA device is reduced up to 43%. This reduces the number of slices (logic blocks) and LUTs, used for the implementation of HD-SPWM. The switching and sampling frequency for the generation of HD-SPWM are 20 kHz and 4 MHz respectively. The code is written in Verilog HDL and simulated in Modelsim and synthesized in Xilinx ISE. The Switching frequency achieved is 20 kHz respectively.