Implementation of Approximate Multipliers Using Exact 4:2 Compressors and Parallel Prefix Adder

Abstract

Multipliers are the key aspects in every arithmetic logic unit where the processing of all computations takes place. Multipliers are also the main components in microprocessor arithmetic units. The ultimate goal in any multiplier is to achieve minimum delay with the least possible number of transistors. In error-tolerant and multimedia applications, approximate computation is used to reduce power consumption, speed, and area while sacrificing accuracy. To solve the partial products, the Wallace Tree and Dada Multipliers are implemented in this work to reduce delay and optimize delays by employing the compressor and parallel prefix adders in the multiplier of the circuit. The multiplier with approximation compressors and parallel-prefix adder will boost power and speed significantly. When compared to existing architectures, this study investigates and two approximation compressors with reduced area, latency and power but comparable accuracy. The proposed design is then compared to existing designs such as Wallace and Dada Multiplier. Xilinx software was used to simulate this multiplier.