Design of Low Power SRAM Cell Using 10Transistors

Abstract

The primary aim of electronics is to design low power devices due to the frequent usage of powered widget. The memory cell operation containing low voltage consumption has become a major interest in designing of memory cells due to its applications in very low energy computing. Due to specification modifications in scaled methodologies, the only critical method is stable operation of SRAM for the success of low voltage design of SRAM. Along with the power and voltage consumption, due to unwanted switching actions of transistors, the access time of the SRAM is also considered as a complex parameter and it is used for different blocks like, designed SRAM cell, access transistors, pre-charge circuit, decoders and sense amplifiers. The conventional 6T SRAM are unable toachievethe less delay and sub threshold operation. The proposed design is designed by using the sleep transistor circuits. The sleep transistor circuits are turned to be ON in active state and in OFF state during passive state. A supply voltage of 1.8V is used which enough for low power applications in energy computing. The designed SRAM cell has conducting pMOS circuit, which can also reduce the total power dissipation. The designed 10T SRAM cell reduces 40.56% of total power and 17.86% of total delay compared with the conventional 6T SRAM cell. The structured SRAM cell is reproduced by utilizing Cadence device of 180nm innovation.