Compensating Threshold Voltage Roll-Off in Nanoscale MOSFET with Parameter Adjustment

Abstract

During last few decades, the Silicon-On-Insulator (SOI) technology has been identified as a possible solution for reducing constrains over transistor miniaturization and to maintain continuous progress in semiconductor chip design industry. The SOI CMOS has numerous advantages over conventional bulk CMOS technology but it is not fully immune of several short channel effects. One of the primary impacts of short channel effects in SOI MOSFET is the degradation of device threshold voltage with decreasing channel length. Such threshold voltage degradation factor with reducing channel length is normally known as threshold voltage roll-off which restricts further scaling of SOI devices. But such roll-off factor can be adjusted by fine tuning the other structural parameters and this fact has been established with theoretical modeling and subsequent simulation under this present work. Under present analysis, a two dimensional generalized analytical threshold voltage model has been presented for nanoscale SOI MOSFET. Threshold voltage performance has been simulated and analyzed for various structural parameters e.g.; channel length, channel doping concentration, gate oxide thickness etc. Finally, how much fine tuning is required for various structural parameters (channel doping concentration and gate oxide thickness) to compensate threshold voltage roll-off factor at various channel length, has been calculated. The simulation results have shown that the unavoidable threshold voltage roll-off effect associated with technology scaling can be minimized by fine-tuning other device parameters.