Journal of VLSI Design and Signal Processing (e-ISSN: 2581-8449)

Design and Analysis of 6T SRAM in 90nm

2023-07-26T10:58:47+0530

This paper aims to design and analyse 6T SRAM in 90nm. All of us desire improved speed for our devices, such as laptops, mobile phones, and computers. Not only our processors but also our memory devices should be fast. In today’s world, more than 80% of chips contain memory elements. Memories are the most valuable part of convenient battery operated digital devices. So, to improve, there are various techniques to design and analyse the SRAM. In this, a conventional SRAM is designed, and the stability, speed, and power consumption are analysed and the gated VDD SRAM is also designed, and the stability, speed, and power consumption are analysed. Based on the resulting and simulated outputs, the Gated VDD SRAMS consumes 8.41% less power than Conventional SRAM and the delay of Gated VDD SRAM is also reduced by 18.052%. Simulations are implemented using the Cadence Virtuoso tool with 90nm technology.

FPGA Implementation of Vending Machine

2023-07-11T14:19:30+0530

This paper aims to create a coin processing system-based vending machine that can handle input coin values and dispense or return change as required, utilizing a single-state machine designed with the Mealy state machine model. To implement this design VHDL is used, which is a hardware description language capable of producing efficient and reliable system development. Xilinx VIVADO 2017.4 software tool is used to simulate and test the system, allowing for efficient debugging of FPGA designs. The system is deployed on a Nexys 4 DDR FPGA Board development board, enabling practical and robust implementation. This particular design offers great versatility, making it suitable for a wide range of applications, such as vending machines, parking meters, and other automated systems that require coin processing. The Mealy state machine model proves to be an efficient and reliable approach to coin processing, and the use of VHDL and FPGA board ensures a practical and effective implementation of the design.

A HW/SW Co-Verification Method for Ask Using FPGA Test

2023-09-26T16:44:17+0530

Field Programmable Gate Arrays (FPGAs) may be used in a wide variety of settings. If weak points in an FPGA can be isolated, then the device's shortcomings may be endured with relative ease. A significant portion of the CLB, IOB, and routing matrix in an FPGA are repeated and regular. As a result, functional testing for FPGA is intended to be consistent and application- and design-neutral. At the moment, strategies for reducing the number of configurations are the main focus of study for FPGA tests. Additionally, manual setting of an FPGA in the usual manner takes time because it must be done. In other words, the quantity of FPGA configurations determines how long an FPGA test takes. The research provides a recommendation and unveils a hardware/software co-verification approach for testing FPGAs. Using the adaptability and visibility of software in combination with the large-speed simulation of the hardware, this process can do comprehensive, automated testing of every Input/output Block (IOB) and custom Configurable Logic Block (CLB) of an FPGA. The proposed technique may detect faulty cells in an FPGA mechanically. Therefore, test efficiency and reliability may be enhanced without devouring the physical work. A hardware-software co-verification network consists of a software simulator and hardware emulation, with the PCI bus acting as the connection between the two. To speed up SOC verification, the hardware emulator maps certain target design modules while the software simulator mimics others. The standard FPGA test strategy's higher costs and requirement for individual PCBs for each FPGA may be avoided.

Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code

2023-12-05T12:02:31+0530

Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code converter (BE-1 converter) has been used in the development of a modified CSA design to overcome the issue. This study presents a practical method for reducing the size and power footprint of the CSA by introducing gate-level changes to the BE-1 converter design. Making use of this alteration, a 4-bit CSA architecture with a BE-1 converter is developed and contrasted with the industry standard CSA design. These designs are evaluated considering their area and power characteristics. The analytical results show that the suggested CSA structure is better than the traditional one and that using a CSA with a BE-1 converter is an efficient way to create a VLSI design.

Analyzing Polar Decoding Approaches: A Comparative Study

2023-12-05T12:13:45+0530

In this paper, we present three methodologies for implementing polar decoders, which are error-correcting codes widely, used in modern communication systems while polar codes show great promise, their implementation can be challenging due to their high computational complexity, which can negatively impact latency and throughput. To address this challenge, we propose three efficient implementations of polar decoders, including processing element-based design, component code-based design, and a special node-based design that identifies specific bit patterns to reduce decoding complexity. We evaluate our proposed decoders by implementing and simulating them using Verilog HDL on the Xilinx platform and compare their performance against existing research papers. Our results demonstrate significant improvements in terms of latency, area throughput, and power dissipation, making them highly suitable for modern communication systems. The special node-based decoder demonstrated the best performance, accomplishing a latency of 32.532ns and a throughput of 245.91 Mbps, using 393 LUTs and an on-chip power dissipation of 3.921 watts. The processing element-based decoder achieved a latency of 40.41 ns and a throughput of 197.79 Mbps, using 445 LUTs and an on-chip power dissipation of 4.142 watts. The component code-based decoder achieved a latency of 33.29 ns and a throughput of 240.27 Mbps, using 470 LUTs and an on-chip power dissipation of 4.933 watts.