Design and Development of Hybridization in Modified Parallel Adder Circuits
Keywords:
Area Efficient, Carry Skip Adder (CSkA), Carry Save Adder (CSA), Carry Increment Adder (CIA), Hybrid Adder, Modified Adder, Power Consumption, Propagation Delay, Ripple Carry Adder (RCA).Abstract
There is always a trade-off between gadget speed, power consumption, and space efficiency in the world of electronics. The majority of electronic circuits contain adder circuitry as they are useful in additions, filter designing, multiplexing, division and many more, further its operational time is very less. As there is a limit on how many transistors can be lowered, it becomes very essential to modify and hybridize a variety of adders as each adder has pros and cons. This review paper deals with a hybrid adder of CSA and CSkA that have been produced by merging them that achieves the benefits of both i.e. CSA is capable of multi-input operations, while CSkA is capable of single-input operations and smaller latency measures in greater bit operation. The CSA-CSkA hybrid adder, the CSA-CIA hybrid adder, and the upgraded CSLA with D-LATCH were all compared in terms of delay, power consumption, and area calculations. The paper is centered on a comparison of various adders. Finally, we determined which adder required the least amount of time, space, and power.
