Construction and Formulation of a MOD 13 Binary Down Counter

Abstract

The technique of designing and synthesizing a MOD 13 binary down counter utilizing 180 nm CMOS technology transistors is described in this paper. Counters are deployed in a variety of scenarios. Some count down from a predetermined value to zero and accordingly alter the state of the output while others start counting from zero and alter the state of the output when it reached the predetermined value. The counter's key parameter is the counter module, which specifies the maximum number of pulses that the counter can count. In addition to tallying up from zero and elevating or incrementing to a predetermined number, tallying "down" from a predetermined value to zero is occasionally done in order to provide an output that activates when the zero count or another pre-set value is reached. As a result, the counter generates a binary number sequence ranging from zero to 2n - 1, where n is the counter's bit capacity. When the maximum value (13) is reached, a modulo 13 counter requires at least 4 bits (triggers) and a reset circuit that resets the counter outputs to zero. The count begins with a combination of 11102 and ends with 00102. Circuit simulations (transient simulations) are performed. After doing an analysis to ensure that the circuit works properly, the integrated circuit layout is completed. Manually connecting the components resulted in a finished product. Finally, the layout is tested to see how it works. The presence of parasitic resistances and capacitances has an impact on the output signals, which is why it is employed to determine the highest clock frequency that can be used (fclk).