Design and Analysis of Delayed Ternary Flip-Flop Implemented with Carbon Nanotube Field Effect Transistor

Abstract

Flip-flops are the basic memory storage element. Its working is based on the arrangement of gates. Its output depends on the input and the clock signal that is provided. Several binary flip-flops based on carbon nanotube are already implemented. When a flip-flop is used in a circuit design, performance efficiency of the digital circuit is improved and power consumption is decreased. In this paper, a proposed flip flop is worked on ternary logic and its performance will be compared with the previously designed flip flops. Here in this paper D flip flop will be designed because it is a basic element used in shift registers. In any D flip flop, the output is always similar to the input but after some finite time interval, that's why it is used in the resistors. Ternary flip flops minimize the interconnection during floor planning because of that naturally the power dissipation inside the circuitry will minimize compared to the binary flip flops. To design the flip flop carbon nanotube field effect transistor will be used. Using the 32nm Stanford CNTFET model and the HSPICE simulator, the proposed D flip-flop is simulated. The results of simulations are based on a power supply voltage of 0.9 volts and an operating frequency of 1 GHz and 100 MHz.