Design and Development of Low Power Array Multiplier

Abstract

A popular topic in research is the development of low-power, high-speed, and regular-layout multipliers. By falling the number of incomplete products created, the multiplier's speed can be increased. The array multiplier is one of many approaches to limiting the number of incomplete products produced during development. An array multiplier half adder was utilized to entirety the carry products in less time. The goal of VLSI circuit inventors is to create high-speed integrated circuits with low power consumption. For the bulk of arithmetic operations, the multiplier, which is the most power-hungry component in digital circuits, is used. The multiplication process is essentially applied in hardware as an add operation and shift. The performance of multipliers has improved as a result of the optimization of the adder. A redesigned full adder with a multiplexer is proposed in this study to achieve reduced multiplier power consumption. The traditional array multiplier structure is utilized to evaluate the efficiency of the proposed architecture. The designs are created in Verilog HDL, and the functionalities are tested using Xilinx simulation. In comparison to current techniques, the recommended multiplier's ASIC synthesis outcomes demonstrate a 15.65% reduction in delay, 35.45% reduction in power ingesting, and 40.75%t reduction in area.

Multipliers will play a significant part in different applications in today's digital signal processing. In the advanced technology, many experts have attempted to create a multiplier with low power and high-speed consumption. Due to the circuit complexity, power consumption and size are two major design factors for multiplier factors. When the outputs of low-power parallel multipliers are common, some columns in the multiplier array can be switched off. The array multiplier can be used in digital picture signal processing, such as finite impulse response (FIR) filters, to reduce power dissipation.