Computational Blocks for DSP Processors with High Speed and Low Power Design

Abstract

Power optimization and speed are critical in today's deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits. This emphasis on low power has resulted in designs that prioritize power dissipation above performance and area. The primary issues in designing circuits down to 100nm are power reduction and power control. Several methodologies and extension designs have been used in the literature for power optimization. Multiplication and accumulation are important digital signal processing (DSP) applications requiring real-time processing. These signal processing procedures' speed and power consumption are the most important performance parameters. Techniques such as Multi threshold (Multi-Vth), Dula-Vth, and others are used to reduce power usage. GDI (Gate diffusion Input) is one of these technologies, which allows digital circuits to have lower logic complexity while reducing power, latency, and area. Several signal processing blocks are created using the GDI (Gate diffusion Input) technique in this paper, including a parallel-prefix adder, Braun multiplier, and Barrel shifter, and speed are compared to traditional CMOS (Complementary Metal Oxide Semiconductor) based designs. Cadence Virtuoso 45nm technology is used to simulate the designs. When compared to CMOS-based devices, simulation studies reveal that GDI-based systems consume less power and have a shorter latency.