High functionality reversible arithmetic logic unit

Abstract

Energy loss is a significant concern in digital logic design, owing to the nearing termination of Moore's Law. An increase in power dissipation impacts not only portability but also the total life span of a device. Many programmes cannot afford to lose this functionality. As a result, reversible logic will be used in future computing to develop power-efficient and compact circuitry. Arithmetic and logic units (ALUs) are essential components of all processors, and creating them with reversible logic is time-consuming. There are several ALU designs that use reversible logic gates in the literature, however, their operations are limited. The primary goal of this study is to propose a novel design of reversible ALU and increase the number of operations available in it. This article compares the suggested ALU to existing designs and shows a 56 percent decrease in gates, a 17 percent reduction in trash lines, a 92 percent reduction in auxiliary lines, and a 53 percent reduction in quantum cost, resulting in increased functionality. The suggested ALU design is written in Verilog HDL, synthesized, and simulated using Xilinx ISE design suite 14.2, an EDA (Electronic Design Automation) tool. The RCViewer+ tool was used to validate the proposed design's quantum cost.