High Speed and Ultra-Low Power Design of 4-Bit Carry Look-Ahead Adder
Keywords:
C4-Bit Adder, Carry-Out Bit, Carry Generation, Carry Look-Ahead, Cadence Virtuoso, Low Power, Performance Parameters, Transistor Count.Abstract
For the carry-out a bit of a 4-bit carry look-ahead (CLA) adder, a new carry generating mechanism is given. The proposed carry-out bit design was constructed and confirmed in the Cadence Virtuoso environment in 90nm technology to test performance. The performance of a 4-bit CLA adder's carry-out bit was compared to that of a typical design. In comparison to the standard CLA design, the proposed design improved propagation delay by 19.69 percent. The average power consumption was reduced by 75.973 percent compared to the normal carry-out bit of the CLA design because to the low transistor count and low dynamic power dissipation. PDP increased by 79.003 percent as a result of this. The proposed CLA carry-out bit is predicted to have a considerable influence on total adder performance due to improvements in performance parameters and a lower transistor count.
