A Novel Design Approach for Compressor Adders

Abstract

Modern technology in the field of VLSI and communication demands for very high-speed processing, lower area and power efficient circuits. We know that multipliers are the key blocks in most of the processing circuits. Different types of multiplier circuits are available nowadays. Among them, Vedic multipliers are considered to be the fastest multipliers. The efficiency of these multipliers is mainly influenced by the adder circuits used for column compression while the partial product reduction. Hence the designs of column compressors or compressor adders play a major role in improving the efficiency of multipliers. In this paper, a novel design is proposed for lower order compressor adders and analyzed. Architectures of 4:3, 5:3, 6:3, 7:3, 8:4, 9:4 & 10:4 compressor adder units are compared with existing logic. The power analysis is done using Cadence Virtuoso tool and area of utilization and delay is analyzed by coding the hardware in Verilog with Xilinx ISE 14.7 series. When applied this in Vedic multiplier circuits the result indicates better speed and overall efficiency for lower order compressor adders.