Design of Low Power High Speed Hybrid Full Adder: A Review
Keywords:
Average Power, CMOS, Hybrid Full Adder (HFA), Low Power, Pass Transistor Logic, Power Delay Product, VLSI, XORAbstract
In this research, I present a new hybrid FA design (a blend of CMOS and transistor logic types) that tries to achieve high speed while consuming minimal power, hence the low PDP designation. Our proposed FA and seven other current FA designs were modelled on the spice with a 45 nm low power model file, a standard test bed, and a standard test pattern (56 input switching), and the impersonation results for eight designs are equivalent. Power outages, distribution delays, and PDP are all issues that need to be addressed. The results of simulations show that our suggested FA design has the shortest broadcast delays and the lowest PDP across the whole power supply and frequency range.
