Design and Analysis of an optimised 4-Bit (CLA) Carry Lookahead Adder

Abstract

This work presents comparative research on an optimised carry look-ahead (CLA) adder which comprises a low-power, high-speed full adder circuit. In the following section, the results of comparing the Conventional Carry look-ahead adder to the Modified and suggested design are noticed and tabulated. The traditional Carry look ahead (CLA) adder has a large number of transistors and high input impedance, both of which have an impact on overall performance. The delay and power consumption of the traditional CLA increases dramatically due to the high input impedance. As a result, new combinations of transistors have been developed, and the Carry-out bit equations have been updated to increase its performance, reduce its size, reduce its power consumption, and reduce the time delay. XOR gates and GDI (gate-diffusion input) AND gates based on hybrid logic can also be employed to reduce transistor count and increase performance. Due to its low transistor count and power dissipation, the observed results showed a 76 percent reduction in average power consumption and a 79.003 percent increase in PDP.