Analysis of a Tolerate Soft Errors in Combinational Circuits

Abstract

Soft mistakes in combinational logic circuits have occurred in recent years, affecting the operation of digital frameworks. As a result, the soft mistake has become a major source of concern for show quality difficulties. This work provides a new strategy for extending soft error tolerance and lowering the failure rate of combinational circuits. A method has been presented for determining the most common minterms in Boolean polynomial math. And different cubes secure these minterms to optimise the logical veiling probability, which lowers the combinational circuit's failure rate. The experimental investigation shows how the probability of a certain combinational circuit failing is reduced.