Comparative Analysis of Low Voltage DTMOS-Based Current Mirrors at 65 nm and Sub 50 nm Technology Nodes

Abstract

This paper presents the characteristics of the current mirrors and shows comparisons among basic Current Mirror (CM), Widlar CM and Cascode CM based on different parameters like output resistance, Trans conductance and gain. This paper is proposed to work at low voltage and has a mixed mode structure. In this paper, Current mirrors are made with the DTMOS technique and show a comparative study based on different parameters at sub 50 nm and 65nm technology nodes. Cascode current with the DTMOS technique is giving better results for the basic current mirror, Widlar current mirror and Cascode CM at sub-50 nm and 65nm technology nodes than that of the 180 nm technology nodes. The cascode current mirror is giving more improvement in the output impedance and shows an output current almost equal to the reference current. This paper has been designed with the LTspice tool at sub-50 nm and 65nm technology nodes without affecting the input and output characteristics of the current mirrors. The current mirrors are drawn and simulated at low voltage in the range of 0.7-0.9V of the supply voltage. In this, an enhanced dynamic threshold MOS transistor is used to improve the characteristic, Trans conductance and gain of the current mirrors. DTMOS is a technique in which the gate-to-source voltage of MOS is the same as the body-to-source voltage and this is equal to the applied input voltage.