ESL design and optimization Method

Abstract

The ever-increasing design complexity of modern-day virtual structures makes it vital to
expand digital device-stage (ESL) methodologies with automation and optimization within
the higher abstraction degree. How the concurrency is modeled inside the utility specification
performs a great role in ESL layout frameworks. The country-of-art concurrent specification
fashions are not appropriate for modeling task-degree concurrent conduct for the hardware
synthesis layout glide. based on the concurrent collection (CnC) model, which presents the
maximum freedom of assignment rescheduling, we endorse challenge-stage facts model
(TLDM), targeted at the project-degree optimization in hardware synthesis for statistics
processing packages. Polyhedral fashions are embedded in TLDM for concise expression of
assignment times, array accesses, and dependencies. Examples are proven to demonstrate the
advantages of our TLDM specification compared to other extensively used concurrency
specs.