Delay optimized 16 X 16 bit Vedic Multiplier - Sri vidya B.V; Kirankumar.T (Journal of Electronic Design Engineering, 2017)
In this paper a comparative study of multiplier is done for speed. The concept used is “UrdhvaTiryagbhyam” algorithm for ancient Indian Vedic mathematics which is utilized for multiplication to improve the speed and area. The approached architecture for a 16X16 multiplier uses 8X8 multiplier along with parallel Carry Save Adders. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The 16×16 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. This multiplier is implemented on Spartan 2 FPGA device XC2S100-5tq144 and also on Virtex-4 vlx15sf363-12. The performance of the proposed algorithm is evaluated based on its speed and device utilization, when implemented on FPGA. We observe, that the speed has enhanced in the proposed multiplier design as compared to the existing multipliers [3]and [4].