D Flip Flop Using AVLG Technique with Static Body Biasing Using Cadence Virtuoso Tool - Dharani S; Asuvanti MA (Journal of Electronic Design Engineering, 2019)
The world is growing at an ultra-fast speed and so is the technology. Today, small devices with maximum efficiency and minimum power are in demand and so came the flip flops. They are used in large number of applications ranging from data storage to microprocessors. In this paper, a new circuit for D flip flop is proposed which uses two techniques, namely, AVL and body biasing techniques on 5 transistor TSPC D flip flop. The D flip flop circuit based on 5 transistor TSPC AVL technique is already existing. The body biasing technique is applied on the already existing circuit in order to minimize the power consumption. The simulations of these circuits are done on Cadence Virtuoso tool using 180nm technology. The detailed description is given in this research paper.