Outline of Twin Precision Multiplier with Low Power and Less Area using Clock Pipelining

Abstract

Configuration of a twin accuracy multiplier, which diminishes the range of the design. The current framework utilizes the twin accuracy multiplier as one n bit multiplier in view of the length of the inputs. Inconvenience of this framework is which involves huge range and requires more power, to tackle this issue another method to diminish the measure of engineering is presented. The framework diminishes half of range and 65% power by utilizing technique called clock pipelining.