Pulsed Latch Technique Shift Registers for High Performance and Low Power Shift Registers

Abstract

This study proposes a straightforward way for replacing flip-flops with pulsed latches while maintaining the same design style. The pulsed-latch approach combines the benefits of latches and flip-flops, allowing for both high speed and low power consumption. The pulsed latch technique was employed in this study to shorten the delay of various shift registers while consuming less power. Low power edge triggered flip-flops are required because of the significant pipelining in VLSI circuitry. The switch from flip-flop to pulsed latch has proven to be a tremendous success in terms of power consumption in these very high-speed VLSI devices.  In the pulse latch mechanism, the proposed technique employs a non-overlapped delayed pulse clock. to eliminate the timing difficulties between the pulsed latches. The functionality of all of the proposed shift registers, which were designed in 90 nm CMOS technology, was verified using Cadence Virtuoso.  The pulse latch technique, according to this research, reduces power consumption in chosen registers and improves the total power delay product. Furthermore, when compared to traditional versions, the proposed registers require less transistors to implement.