Implementation of 64-bit Linear Feedback Shift Register for SS-CDMA

Abstract

This paper has studied the notion of PN sequence and design of linear feedback shift register as applicable to spread spectrum code division multiple access techniques. Maximum length sequence arrangements were presented and utilized as a prologue to some difficult strategies for PN code generation with the assistance of LFSR. In the linear feedback shift register, the feedback is used to modification on every clock cycle. In this paper, we have implemented n-bit LFSR and achieved maximum frequency up to 1300 MHz, which can be used in SS-CDMA. Different parameters are discussed and compared with few existing research papers. Overall parameters were obtained with the help of Xilinx 14.1i by using VHDL.