Low Power and Advanced Image Security
Keywords:
compressive sensing, stream cipher, Block cipher, LFSR, security, Փ-matrix, AES algorithm, FPGA, cryptography, Verilog HDL.Abstract
The main focus is to provide a low power and advanced secure compressive sensing method
for image encryption and decryption. This method combines compressive sensing technique
with stream cipher and block cipher to implement the secure compressive sensing. The use of
stream cipher and block cipher to generate the measurement matrix. AES is one of the
standard algorithm and widely used to encrypt and decrypt the data. The image encryption
and decryption algorithm implemented by using AES 128-bit core. In multibit LFSR system,
bits are shift in every clock cycle where single bit is shift in a conventional LFSR method. The
proposed system implemented using Verilog HDL and simulated by modelsim 6.4 c and
implemented in FPGA spartan 3 XC3S 200 TQ-144.
