Design and Analysis of a New Ultra Low Power Adiabatic VLSI Circuit
Keywords:
Adiabatic logic, CMOS logic, Diode free adiabatic logic (DFAL), Energy recovery, Four phased trapezoidal power clock, Full adder, Low power circuit, Low propagation delay, NAND gateAbstract
Power and energy consumption of electronic devices have become very important. Due to the massive use of electronic devices, it has become important for designing low-power circuits. Low power supply means the threshold voltage of the transistors in electronic devices has to be decreased which in turn causes problems like subthreshold leakage current. The device needs to be velocity saturated and also the threshold voltage becomes more reactive with the temperature change. Also due to the lower voltage supply, gate oxide needs to become thinner causing gate leakage and power dissipation. As a result, various power reduction techniques have come forward. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) are used to design low power circuit. Also scaling of devices has been used. Out of these techniques, one technique was to use time-varying supply voltage instead of the conventional constant voltage supply. With this in mind, the term Adiabatic was introduced for using low-power devices. In this thesis paper, various adiabatic circuits have been explored. And a new type of adiabatic circuit has been proposed for low-power dissipation. Extensive simulation experiments have been carried out using Cadence and LTSpice software. The simulation results suggest the competency of the proposed model.
