Vol. 9 No. 2 (2023)

Articles

• Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform

  M.V.Tejendra Prasad

  39-51

  • Requires Subscription PDF

• Performance Comparison of Pseudo-p and Complementary OTFT-based Combinational Circuits

  Taniza Marium, S. M. Ishraqul Huq, Oli Lowna Baroi, Sateyndra Nath Biswas

  13-24

  • Requires Subscription PDF

• A Novel Channel Routing Using For Minimization of Cross Talk in VLSI

  Dr. M. Lakshmi Narasimha

  25-38

  • Requires Subscription PDF

• Implementation of Logarithmic Square Rooter Using Verilog

  PAVITHRA P

  52-59

  • Requires Subscription PDF

• Design and Analysis of a New Ultra Low Power Adiabatic VLSI Circuit

  Chamak Ganguly, Saeed Hossen Rakib, Farhana Tasnim Aumio, Ariful Islam, S.M.Kifyat Kabir, Raihan Motalib, Satyendra N. Biswas

  1-12

  • Requires Subscription PDF