Implementation of Logarithmic Square Rooter Using Verilog

Abstract

Approximate computing is a widely adopted technique in the field of logarithmic square rooters (LSQ) as it offers significant benefits in terms of energy efficiency. LSQ are computational units designed to calculate square roots, and they can be computationally intensive, leading to high energy consumption and resource requirements. To this issue, a low-complexity LSQ has been developed, utilizing addition and shift operations for integer square root computation. LSQ includes a partial error compensation mechanism and energy accuracy to implement the LSQ and evaluate error analysis by using Verilog. By analyzing the error values and their variations in the error compensator, we evaluate the performance of the LSQ for different input values. The Verilog implementation and simulations demonstrate the effectiveness and suitability of the proposed LSQ design, highlighting its potential benefits in energy-efficient computing systems. This work contributes to the ongoing research in approximate computing and provides valuable insights into the design and optimization of LSQs for real-world applications. The results show that LSQ is depending on input value while error value is varying in the error compensator and analysis of the examples.